The subject system and method are generally directed to optimizing the precision of delaying and recovering signals for various applications. The system and method provide for the selective generation of highly stable signal delay, and for the recovery of transmitted signals in a manner that mitigates certain distortive content (like those due to frequency response, group delay, or the like). The system and method provide for the fine adjustment of signal delay based on a synchronous source, avoiding such asynchronous effects of jitter, signal distortion, and the like.
Various approaches to delaying signals are known in the art. FIG. 1 generally illustrates an approach widely used in the art in various forms. As shown, the approach essentially provides a line of uniform buffer stages interconnected to implement a programmable buffer delay line with selectable delay taps defined at successive interconnection points between buffer stages. The desired delay may simply be tapped off the buffer delay line after the incoming signal has traversed a selected number of buffer stages, having undergone a unit delay with each buffer stage traversed. A multiplexor or other such switching arrangement is used to select the desired delay tapped from the delay line. The delayed signal is then available for various uses, such as correcting a given timing skew between signals in source synchronous interfaces.
Since the propagation delay through each buffer stage defines the unit of delay, the actual signal delay obtained from such buffer delay lines is subject to random, asynchronous effects, and prone to drift. That is, the obtained delay necessarily suffers instability due to process, voltage, and time (PVT) variations. For example, supply noise variations in the buffer delay line circuitry itself yield momentary variations, or jitter, in the delay. Jitter introduced in a sampling clock signal, such as a DQS strobe signal in source synchronous applications, disturbs its time alignment with the data being sampled (DQn data in source synchronous applications), raising the risk of error in sampling the data. Additional factors like the variable capacitor loading on the buffer delay stages often relied upon to speed up or slow down the delays for finer delay resolution only add to the noise sensitivity and overall lack of consistency and predictability in the buffer delay line.
While such instability in buffer delay lines are tolerable in many applications, they are becoming less and less tolerable as electronic systems become increasingly faster in operation and more densely integrated in fabrication. Unless significant remedial measures like adaptive calibration are continually provided, increasing demands for shorter bit lengths and precise synchronization requirements would preclude the use of such buffer delay lines or other similarly unstable, asynchronously deviant forms of delay generation.
Another increasingly prohibitive drawback of buffer delay line approaches for delay generation is the mismatch induced pulse width/duty cycle distortion they introduce in signals as they travel through each delay stage. Each buffer making up a delay stage is typically implemented with MOS transistor devices of different channel type and strength. Random mismatch differences in MOS device strengths invariably alter the rise and fall times of the signal, causing unintended effects. An altered rise time, for instance, affects the point at which the next stage's buffer switches, causing artificial variation in the delay actually contributed by the stage. As illustrated in FIG. 2, the signal's waveform is repeatedly altered as it encounters successive buffer stages, resulting in duty cycle distortion.
Without elaborate measures like the use of different delay lines for rising and falling edges, for example, mismatch induced duty cycle distortion remains a source of random, asynchronous error in delay generation. The problem is only exacerbated by the ongoing trend towards increasingly smaller device geometries.
There is therefore a need for a system and method for selective generation of precise delay for a signal, wherein the generated delay is stable and adjustable in synchronous manner. There is a need for delay generation which minimizes asynchronous sources of deviation in the delay. There is a need for such delay generation for a signal, wherein the distortive content of a signal is mitigated.